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HD74LS259
8-bit Address Latch
REJ03D0471-0200 Rev.2.00 Feb.18.2005 This 8-bit addressable latch is designed for general purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and active-high decoders or demultiplexers. This is multifunctional device capable of storing single-line data in eight addressable latches, and being a 1-to-8 decoder or demultiplexer with active-high outputs. Four distinct modes of operation are selectable by controlling the clear and enable inputs as enumerated in the function table. In the addressable-latch mode, data at the data-in terminal is written into the addressed latch. The addressed latch will follow the data input with all unaddressed latches remaining in their previous states. In the memory mode, latch remains in their previous states and is unaffected by the data or address inputs. To eliminate the possibility of entering erroneous data in the latch, the enable should be held high (inactive) while the address lines are changing. In the clear mode, all outputs are low and unaffected by the address and data inputs.
Features
* Ordering Information
Part Name HD74LS259P HD74LS259FPEL HD74LS259RPEL Package Type DILP-16 pin SOP-16 pin (JEITA) SOP-16 pin (JEDEC) Package Code (Previous Code) PRDP0016AE-B (DP-16FV) PRSP0016DH-B (FP-16DAV) Package Abbreviation -- FP Taping Abbreviation (Quantity) -- EL (2,000 pcs/reel) EL (2,500 pcs/reel)
PRSP0016DG-A RP (FP-16DNV) Note: Please consult the sales office for the above package availability.
Rev.2.00, Feb.18.2005, page 1 of 7
HD74LS259
Pin Arrangement
A Latch Select B C Q0 Q1 Outputs Q2 Q3 GND
1 A 2 3 4 5 6 7 8 B C Q0 Q1 Q2 Q3 Q4 CLR G D Q7 Q6 Q5
16 15 14 13 12 11 10 9
VCC Clear Enable Data Input Q7 Q6 Outputs Q5 Q4
(Top view)
Function Table
Input CLR H H L L G L H L H Output of addressed latch D Qio D L Each other output Qio Qio L L Function Addressable latch Memory 8-line demultiplexer Clear
Select inputs Latch addressed C B A L L L 0 L L H 1 L H L 2 L H H 3 H L L 4 H L H 5 H H L 6 H H H 7 Notes: 1. H; high level, L; low level 2. D; the level at the data input 3. Oio; the level of Qi (i = 0, 1, ... 7, as appropriate) before the indicated steady state input conditions were established.
Rev.2.00, Feb.18.2005, page 2 of 7
HD74LS259
Block Diagram
G D A B C Clear
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Absolute Maximum Ratings
Item Supply voltage Input voltage Power dissipation Storage temperature Symbol VCC VIN PT Tstg Ratings 7 7 400 -65 to +150 Unit V V mW C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item Supply voltage Output current Operating temperature Pulse width Setup time Hold time Data Address Data Address Symbol VCC IOH IOL Topr tw tsu tsu th th Min 4.75 -- -- -20 15 20 20 0 0 Typ 5.00 -- -- 25 -- -- -- -- -- Max 5.25 -400 8 75 -- -- -- -- -- Unit V A mA C ns ns ns ns ns
Rev.2.00, Feb.18.2005, page 3 of 7
HD74LS259
Electrical Characteristics
(Ta = -20 to +75 C)
Item Input voltage Symbol VIH VIL VOH Output voltage VOL IIH IIL min. 2.0 -- 2.7 -- -- -- -- -- -20 -- -- typ.* -- -- -- -- -- max. -- 0.8 -- 0.4 0.5 20 -0.4 0.1 -100 36 -1.5 Unit V V V V A mA mA mA mA V Condition
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = -400 A IOL = 4 mA VCC = 4.75 V, VIH = 2 V, IOL = 8 mA VIL = 0.8 V VCC = 5.25 V, VI = 2.7 V VCC = 5.25 V, VI = 0.4 V VCC = 5.25 V, VI = 7 V VCC = 5.25 V VCC = 5.25 V VCC = 4.75 V, IIN = -18 mA
Input current
II Short-circuit output current IOS -- Supply current** ICC 22 Input clamp voltage VIK -- Notes: * VCC = 5 V, Ta = 25C ** ICC is measured with all outputs open and all inputs grounded.
Switching Characteristics
(VCC = 5 V, Ta = 25C)
Item Symbol tPHL tPLH tPHL tPLH tPHL tPLH tPHL Inputs Clear Data Address Enable Output Q0 to Q7 Q0 to Q7 Q0 to Q7 Q0 to Q7 min. -- -- -- -- -- -- -- typ. 17 20 13 24 18 22 15 max. 27 32 21 38 29 35 24 Unit ns ns ns ns CL = 15 pF, RL = 2 k Condition
Propagation delay time
Rev.2.00, Feb.18.2005, page 4 of 7
HD74LS259
Testing Method
Test Circuit
VCC 4.5V RL Q0 CL Input P.G. Zout = 50 Input P.G. Zout = 50 G Output Q1 Output Q2 Output Q3 Output Clear Q4 Output Q5 Output Q6 Output Q7 Same as Load Circuit 1. Same as Load Circuit 1. Same as Load Circuit 1. Same as Load Circuit 1. Same as Load Circuit 1. Same as Load Circuit 1. Same as Load Circuit 1. Output
Load circuit 1
See Function Table
A B C D
Notes:
1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H).
Waveform
tTLH 90% 1.3 V 10% tPLH tTHL 90% 1.3 V 10% tPHL VOH In phase output tPHL 1.3 V tPLH VOH Out of phase output 1.3 V 1.3 V VOL 1.3 V VOL 3V 0V
Input
Note:
Input pulse; tTLH 15 ns, tTHL 6 ns, PRR = 1 MHz, duty cycle 50%
Rev.2.00, Feb.18.2005, page 5 of 7
HD74LS259
Package Dimensions
JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g
D
16
9
1 0.89 b3
8
Z
E
A1
A
Reference Symbol
Dimension in Millimeters Min Nom 7.62 19.2 6.3 20.32 7.4 5.06 0.51 0.40 0.48 1.30 0.19 0 2.29 2.54 0.25 0.31 15 2.79 1.12 2.54 0.56 Max
e D E
L
1
A A1
e
bp
e1
b c b c
p 3
e Z ( Ni/Pd/Au plating ) L
JEITA Package Code P-SOP16-5.5x10.06-1.27
RENESAS Code PRSP0016DH-B
Previous Code FP-16DAV
MASS[Typ.] 0.24g
*1
D F 9
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
Reference Symbol
*2
c
Dimension in Millimeters Min Nom 10.06 5.50 Max 10.5
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2
8 bp x M L1
A1 A bp b1 c
0.00
0.10
0.20 2.20
0.34
0.40
0.46
0.15
1
0.20
0.25
A
c
HE
0 7.50 7.80 1.27
8 8.00
A1
y L
e x y
0.12 0.15 0.80 0.50
1
Detail F
Z L L 0.70 1.15
0.90
Rev.2.00, Feb.18.2005, page 6 of 7
HD74LS259
JEITA Package Code P-SOP16-3.95x9.9-1.27 RENESAS Code PRSP0016DG-A Previous Code FP-16DNV MASS[Typ.] 0.15g
*1
D 9
F
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
Index mark
*2
E
HE
c
Reference Symbol
Dimension in Millimeters Min Nom 9.90 3.95 Max 10.30
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2
8 bp x M L1
A1 A bp b1 c c
1
0.10
0.14
0.25 1.75
0.34
0.40
0.46
0.15
0.20
0.25
HE
0 5.80 6.10 1.27
8 6.20
A
A1
L y
e x y
0.25 0.15 0.635 0.40
1
Detail F
Z L L 0.60 1.08
1.27
Rev.2.00, Feb.18.2005, page 7 of 7
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